The present invention relates to serial data transmitters and, more particularly, to a serial data transmitter that is capable of operating over a wide range of data rates.
A serial data transmitter has a parallel-to-serial converter, known as a “serializer”, which receives successive multiple-bit data words, converts each data word into a serial representation and concatenates the serial representations to produce a serial bit stream. The serial bit stream output can be single-ended or differential, depending upon the application in which the transmitter is used. The transmitting device also typically includes a receiver that de-serializes incoming data from the transmission media. The serializer typically includes a phase-locked loop (PLL), which locks the rate that each bit is transmitted to a reference clock frequency. The de-serializer also has a PLL, which locks a local clock signal on to the phase and frequency of the data transitions in the serial data stream. The local clock signal is then used capture the incoming data.
As the performance of computer systems increases with each new system generation, serial data communication speed, measured in data rate, typically increases by a factor of two. To maintain backward compatibility with older systems, the serializer and de-serializer are required to operate over wider and wider ranges of data rates. For example, the same serializer and deserializer may be required to operate at 1 gigabits per second (Gb/s), 2 Gb/s or 4 Gb/s, depending on the application in which the device is used. This design requirement forces troublesome design compromises, particularly within the phase-locked loop of the transmitter.
Typically, data is serialized and de-serialized at a frequency that is directly proportional to the data rate. For example, the serializer and deserializer are required to operate twice as fast when transmitting or receiving data at 2 Gb/s than at 1 Gb/s and four times as fast at 4 Gb/s. With the increased range of required data rates, it becomes more and more difficult to design a serializer/deserializer. The design of the PLL that is used for regulating the transmission rate becomes particularly difficult.
For applications employing data rate switching, such as Fibre Channel speed auto-negotiation, switching of the transmit data rate requires a long time period, on the order of hundreds of microseconds, to change the PLL output frequency of the transmitter. In addition, PLL parameters are ideally optimized for jitter performance at a particular data rate. Optimizing the PLL parameters becomes more difficult when the PLL is required to operate at a wide range of data rates.
Also, the design of digital filters in the transmitter becomes more difficult with wider ranges of data rates. Digital filters are commonly used in transmitters for compensating for frequency-dependent losses in a transmission path. While the characteristics of the transmission path are constant, the digital filter characteristics must necessarily change with the data rate. This forces design compromises within the digital filter.
Improved data transmitters are therefore desired, which are capable of operating at a wide range of data rates without compromising the transmitter performance.